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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 38 device structure via backscattered electron (BSE) imaging within the electron microscope (Fig. 3). At this stage, the sample is prepared for further deprocessing through gas-assisted etching (GAE) and delayering in the plasma FIB. The plasma FIB delayeringwas completed in a FERA3 by Tescan. Obvious advantages to thebackside thinningapproach include the ability to eliminate the depackaging and mechanical planarization of upper layers typically requiredprior toplasma FIBdelayeringwhenapproaching fromthe frontside. AnSEMcross sectionof an Intel Skylake i7 processor (Fig. 4) provides a perspective for discussion. Mechanical planarization is often applied to remove the top four to five layers of thedevice, consistingof the largest interconnect structures and the thickest interlayer dielec- tric. Aside fromthe additional processing step, the quality of the subsequent plasma FIB delayering is dictated by the quality of the initial planarization surface. Automated backside thinning yields a superior starting surface and excellent uniformity at the most critical layers. Following the automatedbackside thinning approach, the device is accessed directly at the dense active areas to achieve better uniformity. Note that it is possible to insert the entire die into the FIB-SEM tool for deprocess- ing without the need to remove the die from the packag- ing. Importantly, a backside approach also provides the Fig. 3 (a) 30kVBSE image immediately followingautomated backside thinning. The entire 22 × 24 mm die structure is visible in the image, and the residual thickness varies from 1 to 2 µm. The interaction volumeyields image informationthroughthe residual silicon and into the active silicon. It is apparent that the remaining silicon is thinnest in the lower-right portionof the die. This represents the typical starting conditionprior toGAEanddelayeringwith theplasma FIB. (b) Infrared camera image showing the entire die within the package inserted into the plasma FIB-SEM for deprocessing Fig. 4 SEM cross section of Intel Skylake i7 processor. The frontside of the device is at the top of the image, and the backside is at the bottom of the image, where the density of structures is the highest and the features are of the finest scale. Automated backside processing permits the most direct access to the active areas of the device and yields the highest- quality imaging and uniformity while maintaining maximum device functionality. (a) (b) (continued on page 40)